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Go to where the players in the know go, Privilege Club Casino! http://www.jackpottop-game.net From pllana at par.univie.ac.at Fri Sep 18 10:18:02 2009 From: pllana at par.univie.ac.at (Sabri Pllana) Date: Fri Sep 18 10:18:04 2009 Subject: Final CfP: 2010 International Workshop on Multi-Core Computing Systems (MuCoCoS 2010) Message-ID: <4ab3964d$0$11352$3b214f66@usenet.univie.ac.at> *********************************************************************** Extended paper submission deadline: September 28, 2009 (Firm Deadline) *********************************************************************** 2010 International Workshop on Multi-Core Computing Systems (MuCoCoS 2010) Krakow, Poland, February 15, 2010, in conjunction with CISIS 2010 *********************************************************************** Workshop Proceedings are Published by the IEEE Computer Society Press *********************************************************************** Context ------- The improvement of the processor performance by increasing the clock rate has reached its technological limits. Increasing the number of processor cores rather than clock rate can give better performance and reduce problems like energy consumption, heat dissipation and design complexity. As a result we are now witnessing the emergence of multi-core processors in all markets from laptops and game consoles to servers and supercomputers. However, also from the software development perspective exploiting the full potential of multi-core computing systems is a highly complex and essentially open domain, at the moment forcing application developers to deal with numerous low-level details. Major research efforts are required to streamline the process of software development for multi-core computing systems. Following the successful organization of MuCoCoS 2008 (Barcelona, Spain) and MuCoCoS 2009 (Fukuoka, Japan), MuCoCoS 2010 will be organized in Krakow (Poland). MuCoCoS 2010 is aiming to bring together researchers, developers, practitioners, and users of multi-core computing systems. Topics of Interest ------------------ - The topics of the workshop include but are not limited to: :: homogenous and heterogeneous multi-core architectures :: accelerated multi-core architectures :: interconnection networks :: multi-core embedded systems :: programming languages and models :: algorithms for multi-core computing systems :: applications for multi-core systems :: performance modeling and evaluation of multi-core systems :: simulation of multi-core systems :: design space exploration :: resource usage optimization :: tool-support for multi-core systems :: compilers, runtime and operating systems Submission Guidelines --------------------- - The papers should be prepared using the IEEE CS format, and no longer than 6 pages. Submitted papers will be carefully evaluated based on originality, significance to workshop topics, technical soundness, and presentation quality. - Submission of the paper implies that should the paper be accepted, at least one of the authors will register and present the paper at the workshop. Proceedings of the workshop will be published by IEEE Computer Society Press. The best papers presented at the workshop will be selected for publication in an international journal. - The papers should be submitted electronically via CISIS 2010 website. Important Dates --------------- - Submission: September 28, 2009 (Firm Deadline) - Notification: November 01, 2009 - Final version of the paper: November 14, 2009 - Workshop: February 15, 2010 Workshop Co-chairs ------------------ - Sabri Pllana, University of Vienna, Austria - Leonard Barolli, Fukuoka Institute of Technology, Japan - Fatos Xhafa, Polytechnic University of Catalonia, Spain Program Committee ------------------ - Ajith Abraham, Machine Intelligence Research Labs (MIR Labs), USA - Pavan Balaji, Argonne National Laboratory, USA - Jacob Barhen, Oak Ridge National Laboratory/ Uni. of Tennessee, USA - Siegfried Benkner, University of Vienna, Austria - Fran?ois Bodin, CAPS Entreprise, France - Marian Bubak, AGH Krakow/ Universiteit van Amsterdam, Poland/ Netherlands - Jinjun Chen, Swinburne University of Technology, Australia - Alastair Donaldson, University of Oxford, UK - Martti Forsell, VTT, Finland - Geoffrey Fox, Indiana University, USA - Helen Karatza, Aristotle University of Thessaloniki, Greece - Christoph Kessler, Link?ping University, Sweden - Beniamino Di Martino, Second University of Naples, Italy - Pierre Michaud, IRISA/INRIA, France - Wojciech Mikanik, Silesian University of Technology, Poland - Bernd Mohr, Research Centre J?lich, Germany - Nysret Musliu, Vienna University of Technology, Austria - Jarek Nabrzyski, University of Notre Dame, USA - Raymond Namyst, INRIA Bordeaux Sud-Ouest, France - Lasse Natvig, Norwegian University of Science and Technology, Norway - Victor Pankratius, Universit?t Karlsruhe, Germany - Bertil Schmidt, Nanyang Technological University, Singapore - Leonel Sousa, Technical University of Lisbon, Portugal - Jie Tao, Karlsruhe Institute of Technology, Germany - Jesper Larsson Tr?ff, NEC Laboratories Europe, NEC Europe Ltd, Germany - Gabriel A. Wainer, Carleton University, Canada - Roland Wism?ller, University of Siegen, Germany Keynote Address -------------- MPSoC Design Technologies for Wireless Multimedia Terminals. Rainer Leupers, RWTH Aachen University, Germany Media Sponsor -------------- HPCwire: The Leading Source for Global News and Information covering the entire ecosystem of High Performance Computing (HPC). Contact Person -------------- Sabri Pllana University of Vienna, Austria T. +43 1 4277 39411 F. +43 1 4277 9394 From sergio.valenzuela at evirtual.cl Thu Sep 24 19:40:40 2009 From: sergio.valenzuela at evirtual.cl (Sergio.valenzuela) Date: Thu Sep 24 19:40:41 2009 Subject: Awein and Vista Message-ID: <20090923180436.61745129468C@tron.miserver.cl> Dear Davek: I found this comments when I was trying to find what happened with Awesim. I am Awesim practitioner, I am still using it, it is running under Vista, and with no problems at all. In any way, if you know somthing about Awesim, please let me know, and I will appretiate it very much. Sincerely yours, Sergio Valenzuela M. On Oct 5, 8:19 pm, Abdelhamid BENTAIEB wrote: > Hi every body, > > can someone plz tell me how to get the AWESIM commercial version ? > official detributer ? conatcts .. > thanks in advance Awesim was developed in the early 1990's by Pritsker Corporation. They were purchased by FrontStep. Frontstep was purchased by Mapics. I would guess that Mapics owns the product, but have not heard of any new development in more than 10 years. The only reason that I can think of that you would want to use Awesim at this point is if you have an existing model. Even then, it may not run on current operating systems (but it might). If you are building new models, there are other better choices (like our product ExtendSim). davek -- Consultora Sergio Valenzuela Mayer Modelamiento Virtual & Ing. Industrial www.evirtual.cl Av. Libertad 919 Of 43 - Viqa del Mar From gfursin at gmail.com Sun Sep 27 11:34:00 2009 From: gfursin at gmail.com (Grigori Fursin) Date: Sun Sep 27 11:34:02 2009 Subject: CFP: SMART'10 - 4th Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion Message-ID: <696ca535-d33e-48ce-884d-c9732644005d@p36g2000vbn.googlegroups.com> Apologies if you receive multiple copies of this call. ******************************************************************************** CALL FOR PAPERS 4th Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion (SMART'10) http://ctuning.org/workshop-smart10 January 24, 2010, Pisa, Italy Keynote speaker: Prof. Keith Cooper Rice University, USA (co-located with HiPEAC 2010 Conference) ******************************************************************************** The rapid rate of architectural change and the large diversity of architecture features has made it increasingly difficult for compiler writers to keep pace with microprocessor evolution. This problem has been compounded by the introduction of multicores. Thus, compiler writers have an intractably complex problem to solve. A similar situation arises in processor design where new approaches are needed to help computer architects make the best use of new underlying technologies and to design systems well adapted to future application domains. Recent studies have shown the great potential of statistical machine learning and search strategies for compilation and machine design. The purpose of this workshop is to help consolidate and advance the state of the art in this emerging area of research. The workshop is a forum for the presentation of recent developments in compiler techniques and machine design methodologies based on space exploration and statistical machine learning approaches with the objective of improving performance, parallelism, scalability, and adaptability. Topics of interest include (but are not limited to): Machine Learning, Statistical Approaches, or Search applied to * Empirical Automatic Performance Tuning * Iterative Feedback-Directed Compilation * Self-tuning Programs, Libraries and Language Extensions * Dynamic Optimization/Split Compilation/Adaptive Execution * Adaptive Parallelization * Low-power Optimizations * Adaptive Virtualization * Performance Modeling * Performance Portability * Adaptive Processor and System Architecture * Architecture Simulation and Design Space Exploration * Collective Optimization * Self-tuning Computing Systems * Other Topics relevant to Intelligent and Adaptive Compilers/ Architectures/OS **** Paper Submission Guidelines **** Submitted papers should be original and not published or submitted for publication elsewhere. Papers should use the LNCS format and should be 15 pages maximum. Manuscript preparation guidelines can be found at the LNCS website (http://www.springer.com/computer/lncs, go to "For Authors" and then "Information for LNCS Authors"). Papers must be submitted in the PDF using the workshop submission website. An informal collection of the papers to be presented will be distributed at the workshop. All accepted papers will appear on the workshop website. **** Important Dates **** Final deadline for submission: November 7, 2009 Decision notification: December 14, 2009 Workshop: January 24, 2010 (half-day) Program Chair: David Whalley, Florida State University, USA Organizers: Grigori Fursin, INRIA, France John Cavazos, University of Delaware, USA Steering Committee: Francois Bodin, CAPS Entreprise, France John Cavazos, University of Delaware, USA Lieven Eeckhout, Ghent University, Belgium Grigori Fursin, INRIA, France Michael O'Boyle, University of Edinburgh, UK David Padua, UIUC, USA Olivier Temam, INRIA, France Richard Vuduc, Georgia Tech, USA Program Committee: Denis Barthou, University of Versailles, France Chun Chen, University of Utah, USA Bruce Childers, University of Pittsburgh, USA Rudolf Eigenmann, Purdue University, USA Bjorn Franke, University of Edinburgh, UK Maria Garzaran, UIUC, USA Sabine Glesner, TU Berlin, Germany Engin Ipek, Microsoft Research, USA Prasad Kulkarni, University of Kansas, USA Xiaoming Li, University of Delaware, USA Peter Marwedel, TU Dortmund, Germany Bilha Mendelson, IBM Haifa, Israel Kathryn McKinley, University of Texas, USA Boyana Norris, Argonne National Laboratory, USA Yunheung Paek, Seoul National University, Korea Markus Puschel, Carnegie Mellon University, USA Apan Qasem, Texas State University, USA Martin Schulz, LLNL, USA Xipeng Shen, College of William & Mary, USA Linda Torczon, Rice University, USA R. Clint Whaley, UTSA, USA Chengyong Wu, ICT, China Qing Yi, UTSA, USA ===================================================== Dr. Grigori Fursin, Research Scientist, INRIA, France http://ctuning.org - collaborative performance tuning